(1) Field of the Invention
The invention generally relates to an interconnection process used in semiconductor manufacturing and, more particularly, to a method of forming different width sidewall spacers in the fabrication of integrated circuits.
(2) Description of Prior Art
In sub-quarter-micron MOSFET architectures, it is necessary to use ultra-shallow lightly doped source and drain extension (LDD) regions. Low energy ion implantation is typically used to form LDD regions in the substrate adjacent to the gate structure. Spacers are then formed on the sidewalls of the gate. The spacers protect the channel and LDD regions from a subsequent higher-dose implantation used to form the MOSFET source and drain (S/D).
Referring now to FIG. 1, showing in cross section the prior art of spacer formation, a substrate 10 is provided. The substrate 10 may contain n or p type wells, devices, junctions, and other features (not shown) formed prior to deposition and patterning of the gate oxide 12 and silicon gate 14. The patterned gate oxide 12 and silicon gate 14 form the gate structure of the MOS transistor. A low energy implantation is performed to create the LDD regions 16. A spacer oxide layer 18 is then deposited covering the surface of both the gate structure 12/14 and the exposed substrate 10.
Referring now to FIG. 2, the spacer oxide layer 18 is partially etched away. A portion of the spacer oxide layer 18 remains along the sidewalls of the gate structure 12/14 forming equal width spacers beside the gate. A subsequent implantation (not shown) creating the more heavily doped source and drain (S/D) regions 20 is masked by the sidewall spacers.
In order to mix transistors from different process technologies or with different operating voltages, it is desirable to have different LDD widths for PMOS and NMOS transistors. The width of the LDD region is typically controlled by the width of the gate sidewall spacers. Other approaches for forming different spacer widths exist. U.S. Pat. No. 5,021,354 to Pfiester teaches a method that takes advantage of variation in oxidation of regions with different dopants to form spacers of differing widths. U.S. Pat. No. 5,405,791 to Ahmad et al. teaches a method where equal width spacers are formed. The PMOS device is then masked and an n+ source/drain (S/D) implantation is performed in the NMOS device. The mask is removed and additional oxide is deposited. The NMOS device is then masked and the oxide etched to form the optimal spacer width on the PMOS device. A p+ implantation then forms the S/D regions in the PMOS device. The spacers are then removed and the lightly doped source/drain (LDD) extensions are implanted. Unfortunately, the Ahmad invention cannot be adapted to a self-aligned silicide (salicide) metalization process since the completed device has a covering of silicon nitride. In addition, it has the limitation of only facilitating different spacer widths between NMOS and PMOS devices. U.S. Pat. No. 5,460,998 to Liu teaches a method similar to Ahmad except that the LDD extensions are implanted prior to forming the spacers. U.S. Pat. No. 5,424,572 to Solheim teaches a method that takes advantage of the 8:1 ratio of oxide growth over n+ and p+ regions, respectively. The oxide is grown and then etched, leaving spacers only along the n+ doped sidewalls. U.S. Pat. No. 5,786,247 to Chang et al. teaches a method where spacers are formed in separate steps over the NMOS and PMOS regions allowing individual adjustment of the LDD profiles. U.S. Pat. No. 5,874,330 to Ahn teaches a method where nitride caps are formed over selected devices. The surface is covered with oxide, which is then etched, allowing selective LDD implantation.